organize

[stm32f411ceu6.git] / stm32f411.h

diff --git a/stm32f411.h b/stm32f411.h
index 57ceb900fa00c9ca466fc50a5e0164460087dc74..02799f90f9eaa1c9588c825bf5e5b0a7941c96e3 100644 (file)
--- a/stm32f411.h
+++ b/stm32f411.h
@@ -8,23 +8,31 @@
 /*  AHB1  -------------------------------------------------------------------  */
 
 #define RCC 0x40023800
+#define RCC_CR _MMIO_ (RCC, 0x00)
+#define RCC_CFGR _MMIO_ (RCC, 0x08)
 #define RCC_AHB1ENR _MMIO_ (RCC, 0x30)
+#define RCC_APB2ENR _MMIO_ (RCC, 0x44)
 
 #define GPIOC 0x40020800
 #define GPIOC_MODER _MMIO_ (GPIOC, 0x00)
 #define GPIOC_ODR _MMIO_ (GPIOC, 0x14)
 
+#define GPIOA 0x40020000
+#define GPIOA_MODER _MMIO_ (GPIOA, 0x00)
+#define GPIOA_ODR _MMIO_ (GPIOA, 0x14)
+#define GPIOA_AFRH _MMIO_ (GPIOA, 0x24)
+
 
 /*  APB2  -------------------------------------------------------------------  */
 
-#define USART 0x40011000 /* USART1  */
-#define USART_SR _MMIO_ (USART, 0x00)
-#define USART_DR _MMIO_ (USART, 0x04)
-#define USART_BRR _MMIO_ (USART, 0x08)
-#define USART_CR1 _MMIO_ (USART, 0x0c)
-#define USART_CR2 _MMIO_ (USART, 0x10)
-#define USART_CR3 _MMIO_ (USART, 0x14)
-#define USART_GTPR _MMIO_ (USART, 0x18)
+#define USART1 0x40011000
+#define USART1_SR _MMIO_ (USART1, 0x00)
+#define USART1_DR _MMIO_ (USART1, 0x04)
+#define USART1_BRR _MMIO_ (USART1, 0x08)
+#define USART1_CR1 _MMIO_ (USART1, 0x0c)
+#define USART1_CR2 _MMIO_ (USART1, 0x10)
+#define USART1_CR3 _MMIO_ (USART1, 0x14)
+#define USART1_GTPR _MMIO_ (USART1, 0x18)
 
 
 #endif /* _STM32F411_H_  */