X-Git-Url: https://git.wirehaze.ovh/stm32f411ceu6.git/blobdiff_plain/ca2267d42b6d9e1c8b147aa7685ed91592bfd964..8b035a8bab6355d1addd7440a92116e2e23e4419:/kernel.c?ds=inline

diff --git a/kernel.c b/kernel.c
index 28d576d..1545c6e 100644
--- a/kernel.c
+++ b/kernel.c
@@ -1,52 +1,99 @@
-extern unsigned int _sram_end;
-extern unsigned int _data_vma_start;
-extern unsigned int _data_vma_end;
-extern unsigned int _data_lma_start;
-extern unsigned int _bss_vma_start;
-extern unsigned int _bss_vma_end;
+#include "link.h"
+#include "stm32f411.h"
 
-#define RCC_AHB1 ((volatile unsigned int * const) 0x40023830)
-#define GPIOC_MODER ((volatile unsigned int * const) 0x40020800)
-#define GPIOC_ODR ((volatile unsigned int * const) 0x40020814)
-
-static void
-delay (void)
-{
-  volatile unsigned int i;
-  for (i = 0; i < 500000; i++);
-}
+__attribute__ ((noreturn)) extern void kentry (void);
 
 static void
 reset_handler (void)
 {
   unsigned int *src, *dst;
 
-  /* relocate .data to sram  */
+  /* Set FAULTMASK  */
+  asm ("cpsid f");
+
+  /*  Initialize .data and .bss in SRAM  ------------------------------------  */
+
+  /* Relocate .data section  */
   src = &_data_lma_start;
   dst = &_data_vma_start;
 
   while (dst < &_data_vma_end)
     *(dst++) = *(src++);
 
-  /* initialize .bss  */
+  /* Initialize .bss  */
   dst = &_bss_vma_start;
 
   while (dst < &_bss_vma_end)
     *(dst++) = 0;
 
-  /* blink blink  */
-  *RCC_AHB1 |= (1u << 2);
-  *GPIOC_MODER &= ~(3u << 26);
-  *GPIOC_MODER |= (1u << 26);
+  /*  LED setup  ------------------------------------------------------------  */
+
+  /* GPIOCEN: IO port C clock enable  */
+  *RCC_AHB1ENR |= (1u << 2); /* 1: IO port C clock enabled  */
+  /* MODERy[1:0]: Port x configuration bits (y = 0..15)  */
+  *GPIOC_MODER &= ~(0b11u << 26); /* Clear PC13 bits  */
+  *GPIOC_MODER |= (1u << 26); /* 01: General purpose output mode  */
+
+  /* PC13: 0 = LED on
+   *       1 = LED off  */
+
+  /*  SYSCLK setup  ---------------------------------------------------------  */
+
+  /* HSEBYP: HSE clock bypass  */
+  *RCC_CR &= ~(1u << 18); /* 0: HSE oscillator not bypassed  */
+  /* HSEON: HSE clock enable  */
+  *RCC_CR |= (1u << 16); /* 1: HSE oscillator ON  */
+  /* HSERDY: HSE clock ready flag  */
+  while (!(*RCC_CR & (1u << 17))); /* 0: HSE oscillator not ready  */
+  /* SW: System clock switch  */
+  *RCC_CFGR &= ~(0b11u); /* Clear SW bits  */
+  *RCC_CFGR |= (0b01u); /* 01: HSE oscillator selected as system clock  */
+  /* SWS: System clock switch status  */
+  while ((*RCC_CFGR & (0b11u << 2)) != (0b01u << 2)); /* 01: HSE oscillator used
+                                                         as the system clock  */
+  /* HSION: Internal high-speed clock enable  */
+  *RCC_CR &= ~(1u); /* 0: HSI oscillator OFF  */
+
+  /*  UART setup  -----------------------------------------------------------  */
+
+  /* GPIOAEN: IO port A clock enable  */
+  *RCC_AHB1ENR |= (1u); /* 1: IO port A clock enabled  */
+  /* MODERy[1:0]: Port x configuration bits (y = 0..15)  */
+  *GPIOA_MODER &= ~(0b1111u << 18); /* Clear PA9 and PA10 bits  */
+  *GPIOA_MODER |= (0b1010u << 18); /* 10: Alternate function mode  */
+  /* AFRHy: Alternate function selection for port x bit y (y = 8..15)  */
+  *GPIOA_AFRH &= ~(0b11111111u << 4); /* Clear PA9 and PA10 bits  */
+  *GPIOA_AFRH |= (0b01110111u << 4); /* 0111: AF7  */
+
+  /* PA9: USART1_TX
+   * PA10: USART1_RX  */
+
+  /* USART1EN: USART1 clock enable  */
+  *RCC_APB2ENR |= (1u << 4); /* 1: USART1 clock enabled  */
+  /* UE: USART enable  */
+  *USART1_CR1 |= (1u << 13); /* 1: USART enable  */
+  /* M: Word length  */
+  *USART1_CR1 &= ~(1u << 12); /* 0: 1 Start bit, 8 Data bits, n Stop bit  */
+  /* PCE: Parity control enable  */
+  *USART1_CR1 &= ~(1u << 10); /* 0: Parity control disabled  */
+  /* STOP: STOP bits  */
+  *USART1_CR2 &= ~(0b11u << 12); /* 00: 1 Stop bit  */
+  /* Clock frequency: 25MHz
+   * Desired baud rate: 1.2 KBps
+   * USARTDIV = 1302.0625  */
+  *USART1_BRR = (1302u << 4) | 1u; /* mantissa and fraction (/16)  */
+  /* TE: Transmitter enable  */
+  *USART1_CR1 |= (1u << 3); /* 1: Transmitter is enabled  */
+
+  /*  Jump to kernel entry code  --------------------------------------------  */
+
+  /* Clear FAULTMASK  */
+  asm ("cpsie f");
 
-  while (1)
-    {
-      *GPIOC_ODR ^= (1u << 13);
-      delay ();
-    }
+  kentry ();
 }
 
-__attribute__ ((section (".vtbl"), used))
+__attribute__ ((section (".vector_table"), used))
 static unsigned long const vector_table[] = {
   (unsigned long) &_sram_end,
   (unsigned long) reset_handler,