v4.0/src/DEV/XMAEM/INDEDAT.INC

   1 COMMENT #
   2 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
   3 *                                                                             *
   4 * MODULE NAME     : INDEDAT                                                   *
   5 *                                                                             *
   6 *                                                                             *
   7 *                    5669-196 (C) COPYRIGHT 1988 Microsoft Corporation        *
   8 *                                                                             *
   9 * DESCRIPTIVE NAME: Sytem data structures and equates for 386 XMA emulator    *
  10 *                                                                             *
  11 * STATUS (LEVEL)  : Version (0) Level (1.0)                                   *
  12 *                                                                             *
  13 * FUNCTION        : This file defines the overlays and constants for most of  *
  14 *                   the system data.  The following structures are defined    *
  15 *                   here:                                                     *
  16 *                          The resister save area on our stack                *
  17 *                          80386 Task State Segment (TSS)                     *
  18 *                          The Global Descriptor Table (GDT)                  *
  19 *                          80286 Segment Descriptor                           *
  20 *                          80286 Gate Descriptor                              *
  21 *                          80286 Task State Segment (TSS)                     *
  22 *                                                                             *
  23 * MODULE TYPE     : INC                                                       *
  24 *                                                                             *
  25 * REGISTER USAGE  : 80386 Standard                                            *
  26 *                                                                             *
  27 * RESTRICTIONS    : None                                                      *
  28 *                                                                             *
  29 * DEPENDENCIES    : None                                                      *
  30 *                                                                             *
  31 * EXTERNAL                                                                    *
  32 * REFERENCES      : None                                                      *
  33 *                                                                             *
  34 * CHANGE ACTIVITY :                                                           *
  35 *                                                                             *
  36 * $MAC(INDEDAT) COMP(LOAD) PROD(3270PC) :                                     *
  37 *                                                                             *
  38 * $D0=D0004700 410 870529 D : NEW FOR WSP RELEASE 1.1                         *
  39 * $P1=P0000311 410 870804 D : RENAME MODULES'S LIBRARY FILE TYPE TO "INC"     *
  40 * $P2=P0000410 410 870918 D : RELOCATE DATA TO MAKE ROOM FOR I/O BIT MAP      *
  41 *                                                                             *
  42 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
  43 #
  44
  45 ; BPSTACK is an overlay for our stack when we receive control from an
  46 ; interrupt that we want to handle.  The entry points for these interrupts
  47 ; push a 32 but error  code and the interrupt number (16 bits) onto the stack.
  48 ; Then control goes to INDEEXC which saves the current register values on the
  49 ; stack.  BP is set to point to the beginning of the register save area.  This
  50 ; is the mapping of the resulting stack.
  51
  52 BPSTACK STRUC
  53
  54 BP_ES   DW      0             ; Interrptee's ES
  55 BP_DI   DW      0             ; Interruptee's EDI (32 bit DI)
  56         DW      0             ;
  57 BP_SI   DW      0             ; Interruptee's ESI (32 bit SI)
  58         DW      0             ;
  59 BP_BP   DW      0             ; Interruptee's EBP (32 bit BP)
  60         DW      0             ;
  61 BP_PASP DW      0             ; Interruptee's ESP (32 bit SP)
  62 BP_PSP2 DW      0             ;   (ESP as it was before the PUSHA)
  63 BP_BX   DW      0             ; Interruptee's EBX (32 bit BX)
  64         DW      0             ;
  65 BP_DX   DW      0             ; Interruptee's EDX (32 bit DX)
  66         DW      0             ;
  67 BP_CX   DW      0             ; Interruptee's ECX (32 bit CX)
  68         DW      0             ;
  69 BP_AX   DW      0             ; Interruptee's EAX (32 bit AX)
  70         DW      0             ;
  71 BP_DS   DW      0             ; Interruptee's DS
  72 BP_EX   DW      0             ; Exception ID
  73 BP_EC   DW      0             ; Error Code
  74         DW      0
  75
  76 ; The following values are placed on our stack by the 80386
  77
  78 BP_IP   DW      0             ; Interruptee's EIP (32 bit IP)
  79 BP_IP2  DW      0
  80 BP_CS   DW      0             ; Interruptee's CS (16 bit CS plus 16 bit trash)
  81 BP_CS2  DW      0
  82 BP_FL   DW      0             ; Interruptee's flags (32 bits)
  83 BP_FL2  DW      0
  84 BP_SP   DW      0             ; Interruptee's ESP - saved on an inter-level
  85 BP_SP2  DW      0             ;   interrupt
  86 BP_SS   DW      0             ; Interruptee's SSP - also saved on inter-level
  87 BP_SS2  DW      0             ;   interrupt
  88 BP_VMES DW      0             ; Virtual mode ES
  89 BP_VME2 DW      0
  90 BP_VMDS DW      0             ; Virtual mode DS
  91         DW      0
  92 BP_VMFS DW      0             ; Virtual mode FS
  93         DW      0
  94 BP_VMGS DW      0             ; Virtual mode GS
  95         DW      0
  96 BP_STK  DW      0             ; The rest of the stack
  97
  98 BPSTACK ENDS
  99
 100 BP_START EQU    0             ; Offset from BP of the start of the stack info
 101
 102 SUBTTL   80386 TSS - Task State Segment
 103 PAGE
 104 ;*************************************************
 105 ;                                                *
 106 ;         Start of Debugger's 386 TSS            *
 107 ;                                                *
 108 ;*************************************************
 109
 110 TSS386          STRUC
 111                 DW      0     ; Intel reserved
 112 ETSS_BACK_LINK  DW      0     ; Back link to previous TSS
 113 ETSS_SP0        DW      0     ; ESP for privilege level 0
 114                 DW      0
 115 ETSS_SS0        DW      0     ; SS for privilege level 0
 116                 DW      0     ; Intel reserved
 117 ETSS_SP1        DD      0     ; ESP for privilege level 1
 118 ETSS_SS1        DW      0     ; SS for privilege level 1
 119                 DW      0     ; Intel reserved
 120 ETSS_SP2        DD      0     ; ESP for privilege level 2
 121 ETSS_SS2        DW      0     ; SS for privilege level 2
 122                 DW      0     ; Intel reserved
 123 ETSS_CR3        DD      0     ; CR3 - Page directory base register
 124 ETSS_IP         DW      0     ; Task's EIP
 125                 DW      0
 126 ETSS_FL         DW      0     ; Task's Eflags
 127 ETSS_FL2        DW      0
 128 ETSS_AX         DD      0     ; Task's EAX
 129 ETSS_CX         DD      0     ; Task's ECX
 130 ETSS_DX         DD      0     ; Task's EDX
 131 ETSS_BX         DD      0     ; Task's EBX
 132 ETSS_SP         DW      0     ; Task's ESP
 133                 DW      0
 134 ETSS_BP         DD      0     ; Task's EBP
 135 ETSS_SI         DD      0     ; Task's ESI
 136 ETSS_DI         DD      0     ; Task's EDI
 137 ETSS_ES         DW      0     ; Task's ES
 138                 DW      0     ; Intel reserved
 139 ETSS_CS         DW      0     ; Task's CS
 140                 DW      0     ; Intel reserved
 141 ETSS_SS         DW      0     ; Task's SS
 142                 DW      0     ; Intel reserved
 143 ETSS_DS         DW      0     ; Task's DS
 144                 DW      0     ; Intel reserved
 145 ETSS_FS         DW      0     ; Task's FS
 146                 DW      0     ; Intel reserved
 147 ETSS_GS         DW      0     ; Task's GS
 148                 DW      0     ; Intel reserved
 149 ETSS_LDT        DW      0     ; Selector for task's LDT
 150                 DW      0     ; Intel reserved
 151 ETSS_TRAP       DW      0     ; Trap bit - bit 0 (IBM bit 15)
 152 ETSS_BM_OFFSET  DW      0     ; I/O bit map base
 153 ETSS_AVL        DD      0
 154 TSS386          ENDS
 155 TSS_386_LEN     EQU     68H   ; Length of the TSS
 156 TSS_BM_LEN      EQU     0FFFH-TSS_386_LEN  ; Length of the I/O bit map
 157                               ; The bit map is in the same segment as the TSS
 158                               ;   therefore the descriptor fot the TSS segment
 159                               ;   must have enough room to include the bit map.
 160
 161 SUBTTL  GDT - Global Descriptor Table
 162 PAGE
 163
 164 SUBTTL  GDT - GLOBAL DESCRIPTOR TABLE
 165
 166 ;       THE GLOBAL DESCRIPTOR TABLE DEFINITION
 167 ;       === ====== ========== ===== ==========
 168 ;
 169
 170 GDT_LEN         EQU     512 * 8       ; 512 entries total
 171
 172 GDT_DEF         STRUC
 173
 174 UNUSED_ENTRY    DQ      0             ; Seg reg = 0 illegal - this entry is
 175                                       ; not accessible
 176 GDT_PTR         DQ      0             ; This entry points to this GDT table
 177 MON_IDT_PTR     DQ      0             ; System interrupt descriptor table
 178 RSDA_PTR        DQ      0             ; The real system data area (as opposed
 179                                       ; to the virtual SDA's).  XMA pages
 180                                       ; start here
 181 HUGE_PTR        DQ      0             ; Used to address 0-1M as data
 182
 183 LA_PTR          DQ      0             ; Pointer to the LOADALL area (000800H)
 184
 185 C_BWCRT_PTR     DQ      0             ; Compatible blanck and white display
 186 C_CCRT_PTR      DQ      0             ; Compatible color display
 187 E_CCRT_PTR      DQ      0             ; Enhanced color display (16 bytes)
 188 E_CCRT_PTR2     DQ      0
 189
 190 SYS_ROM_CS      DQ      0             ; CS for system IDT, ROM resident
 191 SYS_ROM_DS      DQ      0             ; DS selector to access above as data
 192 SYS_PATCH_CS    DQ      0             ; CS for system IDT, RAM patch area
 193 SYS_PATCH_DS    DQ      0             ; DS selector to access above as data
 194
 195 V_ROM_CS        DQ      0             ; CS - virtual IDT, ROM resident
 196 V_ROM_DS        DQ      0             ; DS selector to access above as data
 197 V_PATCH_CS      DQ      0             ; CS - virtual IDT, RAM patch area
 198 V_PATCH_DS      DQ      0             ; DS selector to access above as data
 199
 200 ES_TEMP         DQ      0             ; Dynamic pointer for ES
 201 CS_TEMP         DQ      0             ; Dynamic pointer for CS
 202 SS_TEMP         DQ      0             ; Dynamic pointer for SS
 203 DS_TEMP         DQ      0             ; Dynamic pointer for DS
 204
 205 ;       Monitor descriptors
 206
 207 MON_LDTR        DQ      0
 208 MON_DS          DQ      0
 209 MON_ES          DQ      0
 210 MON_SS          DQ      0
 211 MON_CS          DQ      0
 212 MON_TR_SS       DQ      0             ; Task register value for single step
 213 MON_TR_BP       DQ      0             ;  "      "       "    "  breakpoint
 214 MON_TR_HWI      DQ      0             ; Read/write (needs special hardware)
 215 MON_TR_OI       DQ      0             ;  "      "       "    "  control-break
 216
 217 KBD_OWNER_SDA   DQ      0             ; Fast path to keyboard owner's SDA
 218
 219 VTIMER_VECTOR   DB     16 DUP (8 DUP(0))      ; 16 VM timer-related descriptors
 220
 221 ;       Below are the 32 system exception service routine descriptors.
 222
 223 SEX_TSS         DB      32 DUP (8 DUP(0))
 224
 225 ;       Below are the 16 hardware interrupt service routine TSS descriptor
 226 ;       pairs.  The first is suitable for TR loading (i.e. target selector
 227 ;       in the corresponding task gate) and the other is a TSS-as-data
 228 ;       descriptor.
 229
 230 HWI_TSS         DB      16 DUP (16 DUP(0))
 231
 232 ;       This is the descriptor pair for the dispatcher (same format as HWI).
 233
 234 DISPATCH_TASK   DQ      0
 235                 DQ      0
 236
 237 HWI_LDT         DQ      0
 238
 239 BASICS_SEG      DQ      0             ; BASIC's segment (F600)
 240
 241 BIOSS_SEG       DQ      0             ; BIOS's segment (F000)
 242
 243 ;
 244 ;
 245 ;       Any other GDT things go here.  There are around 300 slots left.
 246 ;
 247 ;
 248
 249 RSVD_GDT        DQ      0
 250                 DB     (GDT_LEN - (RSVD_GDT + 8) - (18 * 32)) DUP (0)
 251
 252                                       ; The above leaves space for the
 253                                       ; descriptors needed for 18 VMs
 254
 255 PM_VM           DB     32 DUP (0)     ; Program Manager's virtual machine
 256                                       ; entries.  This will function as
 257                                       ; the highest priority machine.
 258 USER_CS         DQ      0             ; Debugee's code segment
 259 USER_SS         DQ      0             ; Debugee's stack segment
 260 USER_DS         DQ      0             ; Debugee's data segment
 261 USER_ES         DQ      0             ; Debugee's extra segment
 262 USER_TSS        DQ      0             ; Debugee's Task State Segment
 263 USER_TSS_DAT    DQ      0             ; Debugee's TSS as a data segment
 264 USER_LDT        DQ      0             ; Debugee's LDT definition
 265 USER_LDT_DAT    DQ      0             ; Debugee's LDT as a data segment
 266
 267 USER_VMS        DB     14 DUP (32 DUP(0))     ; 16 user VMs
 268
 269 SCRUBBER        DB     32 DUP (0)     ; RAM scrubber - dispatched when no other
 270                                       ; machine has work to do
 271 last_gdt_byte   db     0              ; marker for last GDT byte + 1
 272 GDT_DEF         ENDS
 273
 274 SUBTTL  Virtual Machine Entry
 275 PAGE
 276 ;       Virtual Machine Entry Definition - consists of 4 descriptors
 277 ;
 278 ;               - Pointer to TSS, loadable into the Task Register
 279 ;               - Pointer to TSS, loadable into a regular segment register
 280 ;               - Pointer to the LDT, loadable into the LDT Register
 281 ;               - Pointer to the LDT, loadable into a regular segment register
 282 ;
 283 ;       The first of each pair is for loading into the associated special
 284 ;       system registers,  TR and LDTR.  The second allows dynamic access
 285 ;       and modification of descriptors by the system.
 286
 287 VM_GDT_ENTRY    STRUC
 288
 289 VM_TR           DQ      0             ; TR value for this machine's TSS
 290 TSS_PTR         DQ      0             ; Data pointer to this machine's TSS
 291 VM_LDTR         DQ      0             ; LDTR value for this machine's LDT
 292 LDT_PTR         DQ      0             ; Data pointer to this machine's LDT
 293
 294 VM_GDT_ENTRY    ENDS
 295
 296 SUBTTL  80286 Segment Descriptor
 297 PAGE
 298 ;       DESCRIPTOR TABLE ENTRY STRUCTURES
 299 ;       ========== ===== ===== ==========
 300 ;
 301 ;       Segment Descriptor
 302 ;
 303 ;       The following type of descriptor applies to data segments, code
 304 ;       segments, local, global, and interrupt descriptor table segments,
 305 ;       and task state segments.
 306
 307 DATA_DESC       STRUC
 308
 309 SEG_LIMIT       DW      0             ; Segment limit (1 - 65535 bytes)
 310 BASE_LO_WORD    DW      0             ; 24 bit segment physical address
 311 BASE_HI_BYTE    DB      0             ;   (0 - (16M-1))
 312 DATA_ACC_RIGHTS DB      0             ; Access rights byte
 313 DATA_RESERVED   DW      0             ; Intel reserved
 314
 315 DATA_DESC       ENDS
 316
 317 SHADOW_ID       EQU     DATA_RESERVED ; For garbage collection
 318
 319 SUBTTL  80286 Gate Descriptor
 320 PAGE
 321 ;       80286 Gate Descriptor
 322
 323 ;       The following type of descriptor applies to task gates, call gates,
 324 ;       interrupt gates, and trap gates.
 325
 326 GATE_DESC       STRUC
 327
 328 ENTRY_POINT     DW      0             ; Destination routine entry point
 329                                       ;   within the target segment.
 330                                       ;   This is unused for task gates.
 331 CS_SELECTOR     DW      0             ; Selector for destination segment.
 332                                       ;   For task gates, this must point
 333                                       ;   to a valid task state segment
 334                                       ;   descriptor.  For call, trap, and
 335                                       ;   interrupt gates, this must point
 336                                       ;   to a valid code segment descriptor.
 337                                       ;   The segment defined in that
 338                                       ;   descriptor plus the aforementioned
 339                                       ;   entry-point defines the actual
 340                                       ;   routine address.
 341 WORD_COUNT      DB      0             ; For call gates only - number of
 342                                       ;   words to copy from caller's
 343                                       ;   stack to callee's stack
 344 GATE_ACC_RIGHTS DB      0             ; Access rights byte
 345 GATE_RESERVED   DW      0             ; Intel reserved
 346
 347 GATE_DESC       ENDS
 348
 349 ;       Record for the fields in a selector
 350
 351 SELECTOR        RECORD  INDEX:13,TI:1,RPL:2   ; Standard 286 selector format
 352
 353 SUBTTL  TSS - Task State Segment
 354 PAGE
 355 ;       TASK STATE SEGMENT
 356 ;       ==== ===== =======
 357 ;
 358 ;       There are currently two styles of task state segment (TSS) - one for
 359 ;       VMs and one for the hardware interrupt service routines.  There may
 360 ;       be more later, depending on the needs and/or whims of the Authors
 361 ;       of this and follow-on products.  They will all have one thing in
 362 ;       common - they begin with a 44 byte 286-required machine state data
 363 ;       area.  The first structure below is that area's definition.  All
 364 ;       subsequent colors of TSS will start with space for that data, defined
 365 ;       like so:
 366 ;
 367 ; first_field_name        DB      (TYPE TASK_STATE_286)   DUP     (0)
 368 ;
 369 ;       As a convenience, we use the highest part of the TSS for that
 370 ;       particular task's stack (or in some cases, stacks - for privilege
 371 ;       levels 0, 1, and 2).  The intermediate area is used for task-specific
 372 ;       data.
 373
 374
 375 TASK_STATE_286  STRUC
 376
 377 BACK_LINK       DW      0               ; TSS selector from whence we came
 378 VM_SP0          DW      0               ; SS:SP for CPL 0
 379 VM_SS0          DW      0
 380 VM_SP1          DW      0               ; SS:SP for CPL 1
 381 VM_SS1          DW      0
 382 VM_SP2          DW      0               ; SS:SP for CPL 2
 383 VM_SS2          DW      0
 384 VM_IP           DW      0               ; IP - next instruction to execute
 385 VM_FL           DW      0               ; Flag word
 386 VM_AX           DW      0               ;
 387 VM_CX           DW      0               ; General
 388 VM_DX           DW      0               ;
 389 VM_BX           DW      0               ;
 390 VM_SP           DW      0               ;         Purpose
 391 VM_BP           DW      0               ;
 392 VM_SI           DW      0               ;
 393 VM_DI           DW      0               ;                 Registers
 394 VM_ES           DW      0               ;
 395 VM_CS           DW      0               ; Segment
 396 VM_SS           DW      0               ;          Selectors
 397 VM_DS           DW      0               ;
 398 VM_LDT          DW      0               ; Selector for this task's LDT
 399
 400 TASK_STATE_286  ENDS
 401
 402 ;       Note that the actual stacks for CPLs 2, 1, and 0 are part of the
 403 ;       task state segment.  CPL 3's stack is in its own address space.
 404
 405 SUBTTL  Length Equates
 406 PAGE
 407 ;       Length equates
 408
 409 LA_LEN          EQU     GDT_LEN         ; For new monitor
 410
 411 SIDT_LEN        EQU     256*8           ; Length of the IDT -- 256 interrupt
 412                                         ;   entries, 8 bytes each
 413
 414 TSS_LEN         EQU     68H + 2000H     ; TSS structure length -- 68H for regs
 415                                         ;   2000H for I/O bit map  @P2C
 416
 417 LDT_LEN         EQU     00800H          ; LDT structure length (2K)
 418
 419 VM_ENTRY_LENGTH EQU     TYPE VM_GDT_ENTRY ; Length of a VM entry
 420
 421 VM_ENTRY_WIDTH  EQU     5               ; Shift count for priority. Each
 422                                         ; VM entry = 32 bytes, and SHL 5
 423                                         ; is the same as MUL by 32.
 424 NEXT_DESC       EQU     TYPE DATA_DESC  ; Length of a descriptor
 425
 426 DESC_LEN        EQU     TYPE DATA_DESC  ; Length of a descriptor
 427
 428 DESC_WIDTH      EQU     3               ; Shift count for desc len (8) is 3
 429
 430 PM_VM_SIZE      EQU     01000H          ; Virtual Manager's VM size
 431
 432 MCRT_SIZE       EQU     4*1024          ; Monochrome display size
 433
 434 CCRT_SIZE       EQU     16*1024         ; Compatible color display size
 435
 436 ECCRT_SIZE      EQU     0FFFFH          ; Size of each portion of the enhanced
 437                                         ;   color display buffer
 438
 439 MAX_SEG_LEN     EQU     0FFFFH          ; Maximum segment length = 64K
 440
 441 NULL_SEG_LEN    EQU     00000H          ; Null segment length = 0
 442
 443 THIRTY_TWO_K    EQU     08000H          ; Unit of virtual machine size
 444
 445
 446 SUBTTL  Location Equates
 447 PAGE
 448
 449
 450 ;       Location equates
 451
 452 ;       These items are all pre-allocated, and have no SBDs.  After these,
 453 ;       storage structures are all obtained through the memory manager.
 454
 455 ;-----------------------------------------------------------------------------
 456
 457 ; From here to the end marker, these guys must stay in order as this is
 458 ;  how they are allocated.
 459
 460 GDT_LOC         EQU     0C100H          ; GDT location relative to CS       @P2C
 461
 462 SIDT_LOC        EQU     (GDT_LOC + GDT_LEN)  ; The system IDT is next
 463
 464 DISPATCH_LOC     EQU     (SIDT_LOC + SIDT_LEN)
 465
 466 ; End marker
 467
 468 ;   Monitor equate used in m_state to tell the estep routine that we're
 469 ;    single stepping from within ego.
 470 GO_MODE         EQU     1               ;
 471 ;   Monitor equate used in m_state to tell the hwi_int routine that we're
 472 ;    breaking on a memory read address that's executed
 473 MEMX            EQU     2               ;
 474 ;   Monitor equate used in m_state to tell mon_go that a breakpoint has been
 475 ;    set so enable the breakpoint card
 476 CARD_ENABL      EQU     4               ;
 477 S_MODE          EQU     2000H           ; Selector or segment mode flag
 478
 479 BOOT_IP         EQU     07C00H          ; PC1 IP value for boot
 480
 481 BOOT_CS         EQU     00000H          ; PC1 CS value for boot
 482
 483 BOOT_SS         EQU     00030H          ; PC1 SS value for boot
 484
 485 BOOT_SP         EQU     07FFH           ; PC1 SP value for boot
 486
 487 BOOT_FL         EQU     00200H          ; Interrupts enabled
 488
 489 CS_LO_CACHE     EQU     00000H          ; Code segment
 490
 491 CS_HI_CACHE     EQU     000H            ;   compatible cache
 492
 493 SS_LO_CACHE     EQU     00300H          ; Stack segment
 494
 495 SS_HI_CACHE     EQU     000H            ;   compatible cache
 496
 497 OTHER_CACHE     EQU     00000H          ; GP zero cache
 498
 499 SUBTTL  Display Equates
 500 PAGE
 501
 502 ;       The next equates are system definitions for display buffer addresses.
 503
 504
 505 MCRT@_LO        EQU     0000H           ;
 506                                         ; Monochrome display address
 507 MCRT@_HI        EQU     0BH             ; (0B0000H)
 508
 509 CCRT@_LO        EQU     8000H           ;
 510                                         ; Compatible color display address
 511 CCRT@_HI        EQU     0BH             ; (0B8000H)
 512
 513 ECCRT@_LO_LO    EQU     0000H           ;
 514                                         ; Enhanced color display address -
 515 ECCRT@_LO_HI    EQU     0AH             ;   lower 64K (0A0000H)
 516
 517 ECCRT@_HI_LO    EQU     0000H           ;
 518                                         ; Enhanced color display address -
 519 ECCRT@_HI_HI    EQU     0CH             ;   upper 64K (0C0000H)
 520
 521
 522 ;       Code segment addresses
 523
 524
 525 CSEG@_LO        EQU     0000H           ;
 526                                         ; ROM code segment address
 527 CSEG@_HI        EQU     0EH             ; (0E0000H)
 528
 529 NSEG@_LO        EQU     0000H           ;
 530                                         ; Null segment address
 531 NSEG@_HI        EQU     00H             ;
 532
 533 VIRTUAL_ENABLE  EQU     0000000000000001B
 534
 535 SUBTTL