v4.0/src/MEMM/MEMM/TRAPDEF.ASM

   1
   2
   3         page    58,132
   4 ;******************************************************************************
   5         title   TRAPDEF.ASM - I/O trap Dispatch table
   6 ;******************************************************************************
   7 ;
   8 ;   (C) Copyright MICROSOFT Corp. 1986
   9 ;
  10 ;   Title:    MEMM.EXE - MICROSOFT Expanded Memory Manager 386 Driver
  11 ;
  12 ;   Module:   TRAPDEF.ASM - I/O trap Dispatch table
  13 ;
  14 ;   Version:  0.04
  15 ;
  16 ;   Date:     July 1, 1986
  17 ;
  18 ;   Author:
  19 ;
  20 ;******************************************************************************
  21 ;
  22 ;   Change log:
  23 ;
  24 ;     DATE    REVISION                  DESCRIPTION
  25 ;   --------  --------  -------------------------------------------------------
  26 ;   08/11/86            Split from IOTrap.asm
  27 ;
  28 ;   7/26/88             Added Trap handler entries for DMA ports on Channel 4
  29 ;                        - Jaywant H Bharadwaj
  30 ;
  31 ;******************************************************************************
  32 ;
  33 .lfcond                                 ; list false conditionals
  34 .386p
  35         page
  36 ;******************************************************************************
  37 ;                       P U B L I C   D E C L A R A T I O N S
  38 ;******************************************************************************
  39 ;
  40         public  IOTrap_Tab              ; dispatches I/O trap handlers
  41         public  IOT_BadT                ; Unknown port trap routine
  42         public  IOT_OEM                 ; OEM specific port emulation
  43
  44         page
  45 ;******************************************************************************
  46 ;                       L O C A L   C O N S T A N T S
  47 ;******************************************************************************
  48 ;
  49 ; % - how many of these are actually needed?
  50 ; % - Need any includes from Win/386 DMA code - trapdef.asm ?
  51
  52         include VDMseg.inc
  53         include VDMsel.inc
  54         include desc.inc
  55         include elim.inc
  56         include page.inc
  57         include oemdep.inc
  58         include instr386.inc
  59         include vm386.inc
  60 ;
  61 ;******************************************************************************
  62 ;                       E X T E R N A L   R E F E R E N C E S
  63 ;******************************************************************************
  64 ;
  65
  66 _DATA   segment
  67 ;extrn  _map_size:byte          ; # of mapping registers used
  68 ;extrn  LIMP_Addr:word
  69 _DATA   ends
  70
  71 _TEXT   segment
  72 ;
  73 extrn   RRP_Handler:near
  74 extrn   A20_Handler:near        ; Kybd Data port - A20 watch
  75 extrn   DMABase0:near           ;  DMA base register for Channel 0
  76 extrn   DMABase1:near           ;  DMA base register for Channel 1
  77 extrn   DMABase2:near           ;  DMA base register for Channel 2
  78 extrn   DMABase3:near           ;  DMA base register for Channel 3
  79 extrn   DMABase5:near           ;  DMA base register for Channel 5
  80 extrn   DMABase6:near           ;  DMA base register for Channel 6
  81 extrn   DMABase7:near           ;  DMA base register for Channel 7
  82 extrn   DMACnt0:near            ;  DMA count register for Channel 0
  83 extrn   DMACnt1:near            ;  DMA count register for Channel 1
  84 extrn   DMACnt2:near            ;  DMA count register for Channel 2
  85 extrn   DMACnt3:near            ;  DMA count register for Channel 3
  86 extrn   DMACnt5:near            ;  DMA count register for Channel 5
  87 extrn   DMACnt6:near            ;  DMA count register for Channel 6
  88 extrn   DMACnt7:near            ;  DMA count register for Channel 7
  89 extrn   DMAPg0:near             ;  DMA page register for Channel 0
  90 extrn   DMAPg1:near             ;  DMA page register for Channel 1
  91 extrn   DMAPg2:near             ;  DMA page register for Channel 2
  92 extrn   DMAPg3:near             ;  DMA page register for Channel 3
  93 extrn   DMAPg5:near             ;  DMA page register for Channel 5
  94 extrn   DMAPg6:near             ;  DMA page register for Channel 6
  95 extrn   DMAPg7:near             ;  DMA page register for Channel 7
  96 extrn   DMAClrFF1:near          ;  clear flip-flop cmd for channels 0-3
  97 extrn   DMAClrFF2:near          ;  clear flip-flop cmd for channels 5-7
  98 extrn   DMAMode1:near           ;  Mode register for channels 0-3
  99 extrn   DMAMode2:near           ;  Mode register for channels 4-7
 100
 101 _TEXT   ends
 102
 103 ;******************************************************************************
 104 ;                       S E G M E N T   D E F I N I T I O N
 105 ;******************************************************************************
 106
 107 ;
 108 ;------------------------------------------------------------------------------
 109 _TEXT   segment
 110         assume  cs:_TEXT, ds:DGROUP, es:DGROUP, ss:DGROUP
 111 ;
 112 ;   IOTrapTab
 113 ;       One entry per port in the I/O space from 00h to FFh.
 114 ;       Note that ports not specifically mapped otherwise(by IOT_OEM or
 115 ;       LIM emulation and whose least significant 10 bits are less than
 116 ;       100h are also dispatched through this table(upper 6 bits assumed to
 117 ;       be intended as zero since some earlier systems only had 10 bits of
 118 ;       I/O addressing).
 119 ;
 120 IOTrap_Tab      label   word
 121         dw      offset _TEXT:DMAbase0  ;  0 DMA base register for Channel 0
 122         dw      offset _TEXT:DMACnt0   ;  1 DMA count register for Channel 0
 123         dw      offset _TEXT:DMABase1  ;  2 DMA base register for Channel 1
 124         dw      offset _TEXT:DMACnt1   ;  3 DMA count register for Channel 1
 125         dw      offset _TEXT:DMABase2  ;  4 DMA base register for Channel 2
 126         dw      offset _TEXT:DMACnt2   ;  5 DMA count register for Channel 2
 127         dw      offset _TEXT:DMABase3  ;  6 DMA base register for Channel 3
 128         dw      offset _TEXT:DMACnt3   ;  7 DMA count register for Channel 3
 129         dw      offset _TEXT:IOT_BadT  ;  8
 130         dw      offset _TEXT:IOT_BadT  ;  9
 131         dw      offset _TEXT:IOT_BadT  ;  a
 132         dw      offset _TEXT:DMAMode1  ;  b DMA Mode Register for for Ch 0-3
 133         dw      offset _TEXT:DMAClrFF1   ;  c clear flip-flop cmd for channels 0-3
 134         dw      offset _TEXT:IOT_BadT  ;  d
 135         dw      offset _TEXT:IOT_BadT  ;  e
 136         dw      offset _TEXT:IOT_BadT  ;  f
 137         dw      offset _TEXT:IOT_BadT  ; 10
 138         dw      offset _TEXT:IOT_BadT  ; 11
 139         dw      offset _TEXT:IOT_BadT  ; 12
 140         dw      offset _TEXT:IOT_BadT  ; 13
 141         dw      offset _TEXT:IOT_BadT  ; 14
 142         dw      offset _TEXT:IOT_BadT  ; 15
 143         dw      offset _TEXT:IOT_BadT  ; 16
 144         dw      offset _TEXT:IOT_BadT  ; 17
 145         dw      offset _TEXT:IOT_BadT  ; 18
 146         dw      offset _TEXT:IOT_BadT  ; 19
 147         dw      offset _TEXT:IOT_BadT  ; 1a
 148         dw      offset _TEXT:IOT_BadT  ; 1b
 149         dw      offset _TEXT:IOT_BadT  ; 1c
 150         dw      offset _TEXT:IOT_BadT  ; 1d
 151         dw      offset _TEXT:IOT_BadT  ; 1e
 152         dw      offset _TEXT:IOT_BadT  ; 1f
 153         dw      offset _TEXT:IOT_BadT  ; 20
 154         dw      offset _TEXT:IOT_BadT  ; 21
 155         dw      offset _TEXT:IOT_BadT  ; 22
 156         dw      offset _TEXT:IOT_BadT  ; 23
 157         dw      offset _TEXT:IOT_BadT  ; 24
 158         dw      offset _TEXT:IOT_BadT  ; 25
 159         dw      offset _TEXT:IOT_BadT  ; 26
 160         dw      offset _TEXT:IOT_BadT  ; 27
 161         dw      offset _TEXT:IOT_BadT  ; 28
 162         dw      offset _TEXT:IOT_BadT  ; 29
 163         dw      offset _TEXT:IOT_BadT  ; 2a
 164         dw      offset _TEXT:IOT_BadT  ; 2b
 165         dw      offset _TEXT:IOT_BadT  ; 2c
 166         dw      offset _TEXT:IOT_BadT  ; 2d
 167         dw      offset _TEXT:IOT_BadT  ; 2e
 168         dw      offset _TEXT:IOT_BadT  ; 2f
 169         dw      offset _TEXT:IOT_BadT  ; 30
 170         dw      offset _TEXT:IOT_BadT  ; 31
 171         dw      offset _TEXT:IOT_BadT  ; 32
 172         dw      offset _TEXT:IOT_BadT  ; 33
 173         dw      offset _TEXT:IOT_BadT  ; 34
 174         dw      offset _TEXT:IOT_BadT  ; 35
 175         dw      offset _TEXT:IOT_BadT  ; 36
 176         dw      offset _TEXT:IOT_BadT  ; 37
 177         dw      offset _TEXT:IOT_BadT  ; 38
 178         dw      offset _TEXT:IOT_BadT  ; 39
 179         dw      offset _TEXT:IOT_BadT  ; 3a
 180         dw      offset _TEXT:IOT_BadT  ; 3b
 181         dw      offset _TEXT:IOT_BadT  ; 3c
 182         dw      offset _TEXT:IOT_BadT  ; 3d
 183         dw      offset _TEXT:IOT_BadT  ; 3e
 184         dw      offset _TEXT:IOT_BadT  ; 3f
 185         dw      offset _TEXT:IOT_BadT  ; 40
 186         dw      offset _TEXT:IOT_BadT  ; 41
 187         dw      offset _TEXT:IOT_BadT  ; 42
 188         dw      offset _TEXT:IOT_BadT  ; 43
 189         dw      offset _TEXT:IOT_BadT  ; 44
 190         dw      offset _TEXT:IOT_BadT  ; 45
 191         dw      offset _TEXT:IOT_BadT  ; 46
 192         dw      offset _TEXT:IOT_BadT  ; 47
 193         dw      offset _TEXT:IOT_BadT  ; 48
 194         dw      offset _TEXT:IOT_BadT  ; 49
 195         dw      offset _TEXT:IOT_BadT  ; 4a
 196         dw      offset _TEXT:IOT_BadT  ; 4b
 197         dw      offset _TEXT:IOT_BadT  ; 4c
 198         dw      offset _TEXT:IOT_BadT  ; 4d
 199         dw      offset _TEXT:IOT_BadT  ; 4e
 200         dw      offset _TEXT:IOT_BadT  ; 4f
 201         dw      offset _TEXT:IOT_BadT  ; 50
 202         dw      offset _TEXT:IOT_BadT  ; 51
 203         dw      offset _TEXT:IOT_BadT  ; 52
 204         dw      offset _TEXT:IOT_BadT  ; 53
 205         dw      offset _TEXT:IOT_BadT  ; 54
 206         dw      offset _TEXT:IOT_BadT  ; 55
 207         dw      offset _TEXT:IOT_BadT  ; 56
 208         dw      offset _TEXT:IOT_BadT  ; 57
 209         dw      offset _TEXT:IOT_BadT  ; 58
 210         dw      offset _TEXT:IOT_BadT  ; 59
 211         dw      offset _TEXT:IOT_BadT  ; 5a
 212         dw      offset _TEXT:IOT_BadT  ; 5b
 213         dw      offset _TEXT:IOT_BadT  ; 5c
 214         dw      offset _TEXT:IOT_BadT  ; 5d
 215         dw      offset _TEXT:IOT_BadT  ; 5e
 216         dw      offset _TEXT:IOT_BadT  ; 5f
 217         dw      offset _TEXT:A20_Handler        ; A20 watch on kybd data port
 218         dw      offset _TEXT:IOT_BadT  ; 61
 219         dw      offset _TEXT:IOT_BadT  ; 62
 220         dw      offset _TEXT:IOT_BadT  ; 63
 221         dw      offset _TEXT:A20_Handler        ; A20 watch on kybd cmd port
 222         dw      offset _TEXT:IOT_BadT  ; 65
 223         dw      offset _TEXT:IOT_BadT  ; 66
 224         dw      offset _TEXT:IOT_BadT  ; 67
 225         dw      offset _TEXT:IOT_BadT  ; 68
 226         dw      offset _TEXT:IOT_BadT  ; 69
 227         dw      offset _TEXT:IOT_BadT  ; 6a
 228         dw      offset _TEXT:IOT_BadT  ; 6b
 229         dw      offset _TEXT:IOT_BadT  ; 6c
 230         dw      offset _TEXT:IOT_BadT  ; 6d
 231         dw      offset _TEXT:IOT_BadT  ; 6e
 232         dw      offset _TEXT:IOT_BadT  ; 6f
 233         dw      offset _TEXT:IOT_BadT  ; 70
 234         dw      offset _TEXT:IOT_BadT  ; 71
 235         dw      offset _TEXT:IOT_BadT  ; 72
 236         dw      offset _TEXT:IOT_BadT  ; 73
 237         dw      offset _TEXT:IOT_BadT  ; 74
 238         dw      offset _TEXT:IOT_BadT  ; 75
 239         dw      offset _TEXT:IOT_BadT  ; 76
 240         dw      offset _TEXT:IOT_BadT  ; 77
 241         dw      offset _TEXT:IOT_BadT  ; 78
 242         dw      offset _TEXT:IOT_BadT  ; 79
 243         dw      offset _TEXT:IOT_BadT  ; 7a
 244         dw      offset _TEXT:IOT_BadT  ; 7b
 245         dw      offset _TEXT:IOT_BadT  ; 7c
 246         dw      offset _TEXT:IOT_BadT  ; 7d
 247         dw      offset _TEXT:IOT_BadT  ; 7e
 248         dw      offset _TEXT:IOT_BadT  ; 7f
 249         dw      offset _TEXT:IOT_BadT  ; 80
 250         dw      offset _TEXT:DMAPg2    ; 81 DMA page register for Channel 2
 251         dw      offset _TEXT:DMAPg3    ; 82 DMA page register for Channel 3
 252         dw      offset _TEXT:DMAPg1    ; 83 DMA page register for Channel 1
 253         dw      offset _TEXT:RRP_Handler        ; return to real port
 254         dw      offset _TEXT:RRP_Handler        ; return to real port
 255         dw      offset _TEXT:IOT_BadT  ; 86
 256         dw      offset _TEXT:DMAPg0    ; 87 DMA page register for Channel 0
 257         dw      offset _TEXT:IOT_BadT  ; 88
 258         dw      offset _TEXT:DMAPg6    ; 89 DMA page register for Channel 6
 259         dw      offset _TEXT:DMAPg7    ; 8a DMA page register for Channel 7
 260         dw      offset _TEXT:DMAPg5    ; 8b DMA page register for Channel 5
 261         dw      offset _TEXT:IOT_BadT  ; 8c
 262         dw      offset _TEXT:IOT_BadT  ; 8d
 263         dw      offset _TEXT:IOT_BadT  ; 8e
 264         dw      offset _TEXT:IOT_BadT  ; 8f
 265         dw      offset _TEXT:IOT_BadT  ; 90
 266         dw      offset _TEXT:DMAPg2    ; 91 DMA page register for Channel 2
 267         dw      offset _TEXT:DMAPg3    ; 92 DMA page register for Channel 3
 268         dw      offset _TEXT:DMAPg1    ; 93 DMA page register for Channel 1
 269         dw      offset _TEXT:IOT_BadT  ; 94
 270         dw      offset _TEXT:IOT_BadT  ; 95
 271         dw      offset _TEXT:IOT_BadT  ; 96
 272         dw      offset _TEXT:IOT_BadT  ; 97 DMA page register for Channel 0
 273         dw      offset _TEXT:IOT_BadT  ; 98
 274         dw      offset _TEXT:DMAPg6    ; 99 DMA page register for Channel 6
 275         dw      offset _TEXT:DMAPg7    ; 9a DMA page register for Channel 7
 276         dw      offset _TEXT:DMAPg5    ; 9b DMA page register for Channel 5
 277         dw      offset _TEXT:IOT_BadT  ; 9c
 278         dw      offset _TEXT:IOT_BadT  ; 9d
 279         dw      offset _TEXT:IOT_BadT  ; 9e
 280         dw      offset _TEXT:IOT_BadT  ; 9f
 281         dw      offset _TEXT:IOT_BadT  ; a0
 282         dw      offset _TEXT:IOT_BadT  ; a1
 283         dw      offset _TEXT:IOT_BadT  ; a2
 284         dw      offset _TEXT:IOT_BadT  ; a3
 285         dw      offset _TEXT:IOT_BadT  ; a4
 286         dw      offset _TEXT:IOT_BadT  ; a5
 287         dw      offset _TEXT:IOT_BadT  ; a6
 288         dw      offset _TEXT:IOT_BadT  ; a7
 289         dw      offset _TEXT:IOT_BadT  ; a8
 290         dw      offset _TEXT:IOT_BadT  ; a9
 291         dw      offset _TEXT:IOT_BadT  ; aa
 292         dw      offset _TEXT:IOT_BadT  ; ab
 293         dw      offset _TEXT:IOT_BadT  ; ac
 294         dw      offset _TEXT:IOT_BadT  ; ad
 295         dw      offset _TEXT:IOT_BadT  ; ae
 296         dw      offset _TEXT:IOT_BadT  ; af
 297         dw      offset _TEXT:IOT_BadT  ; b0
 298         dw      offset _TEXT:IOT_BadT  ; b1
 299         dw      offset _TEXT:IOT_BadT  ; b2
 300         dw      offset _TEXT:IOT_BadT  ; b3
 301         dw      offset _TEXT:IOT_BadT  ; b4
 302         dw      offset _TEXT:IOT_BadT  ; b5
 303         dw      offset _TEXT:IOT_BadT  ; b6
 304         dw      offset _TEXT:IOT_BadT  ; b7
 305         dw      offset _TEXT:IOT_BadT  ; b8
 306         dw      offset _TEXT:IOT_BadT  ; b9
 307         dw      offset _TEXT:IOT_BadT  ; ba
 308         dw      offset _TEXT:IOT_BadT  ; bb
 309         dw      offset _TEXT:IOT_BadT  ; bc
 310         dw      offset _TEXT:IOT_BadT  ; bd
 311         dw      offset _TEXT:IOT_BadT  ; be
 312         dw      offset _TEXT:IOT_BadT  ; bf
 313         dw      offset _TEXT:IOT_BadT  ; c0 DMA base register for Channel 4
 314         dw      offset _TEXT:IOT_BadT  ; c1
 315         dw      offset _TEXT:IOT_BadT  ; c2 DMA count register for Channel 4
 316         dw      offset _TEXT:IOT_BadT  ; c3
 317         dw      offset _TEXT:DMABase5  ; c4 DMA base register for Channel 5
 318         dw      offset _TEXT:IOT_BadT  ; c5
 319         dw      offset _TEXT:DMACnt5   ; c6 DMA count register for Channel 5
 320         dw      offset _TEXT:IOT_BadT  ; c7
 321         dw      offset _TEXT:DMABase6  ; c8 DMA base register for Channel 6
 322         dw      offset _TEXT:IOT_BadT  ; c9
 323         dw      offset _TEXT:DMACnt6   ; ca DMA count register for Channel 6
 324         dw      offset _TEXT:IOT_BadT  ; cb
 325         dw      offset _TEXT:DMABase7  ; cc DMA base register for Channel 7
 326         dw      offset _TEXT:IOT_BadT  ; cd
 327         dw      offset _TEXT:DMACnt7   ; ce DMA count register for Channel 7
 328         dw      offset _TEXT:IOT_BadT  ; cf
 329         dw      offset _TEXT:IOT_BadT  ; d0
 330         dw      offset _TEXT:IOT_BadT  ; d1
 331         dw      offset _TEXT:IOT_BadT  ; d2
 332         dw      offset _TEXT:IOT_BadT  ; d3
 333         dw      offset _TEXT:IOT_BadT  ; d4
 334         dw      offset _TEXT:IOT_BadT  ; d5
 335         dw      offset _TEXT:DMAMode2  ; d6 DMA Mode Register for channels 4-7
 336         dw      offset _TEXT:IOT_BadT  ; d7
 337         dw      offset _TEXT:DMAClrFF2   ; d8 clear flip-flop cmd for channels 5-7
 338         dw      offset _TEXT:IOT_BadT  ; d9
 339         dw      offset _TEXT:IOT_BadT  ; da
 340         dw      offset _TEXT:IOT_BadT  ; db
 341         dw      offset _TEXT:IOT_BadT  ; dc
 342         dw      offset _TEXT:IOT_BadT  ; dd
 343         dw      offset _TEXT:IOT_BadT  ; de
 344         dw      offset _TEXT:IOT_BadT  ; df
 345         dw      offset _TEXT:IOT_BadT  ; e0
 346         dw      offset _TEXT:IOT_BadT  ; e1
 347         dw      offset _TEXT:IOT_BadT  ; e2
 348         dw      offset _TEXT:IOT_BadT  ; e3
 349         dw      offset _TEXT:IOT_BadT  ; e4
 350         dw      offset _TEXT:IOT_BadT  ; e5
 351         dw      offset _TEXT:IOT_BadT  ; e6
 352         dw      offset _TEXT:IOT_BadT  ; e7
 353         dw      offset _TEXT:IOT_BadT  ; e8
 354         dw      offset _TEXT:IOT_BadT  ; e9
 355         dw      offset _TEXT:IOT_BadT  ; ea
 356         dw      offset _TEXT:IOT_BadT  ; eb
 357         dw      offset _TEXT:IOT_BadT  ; ec
 358         dw      offset _TEXT:IOT_BadT  ; ed
 359         dw      offset _TEXT:IOT_BadT  ; ee
 360         dw      offset _TEXT:IOT_BadT  ; ef
 361         dw      offset _TEXT:IOT_BadT  ; f0
 362         dw      offset _TEXT:IOT_BadT  ; f1
 363         dw      offset _TEXT:IOT_BadT  ; f2
 364         dw      offset _TEXT:IOT_BadT  ; f3
 365         dw      offset _TEXT:IOT_BadT  ; f4
 366         dw      offset _TEXT:IOT_BadT  ; f5
 367         dw      offset _TEXT:IOT_BadT  ; f6
 368         dw      offset _TEXT:IOT_BadT  ; f7
 369         dw      offset _TEXT:IOT_BadT  ; f8
 370         dw      offset _TEXT:IOT_BadT  ; f9
 371         dw      offset _TEXT:IOT_BadT  ; fa
 372         dw      offset _TEXT:IOT_BadT  ; fb
 373         dw      offset _TEXT:IOT_BadT  ; fc
 374         dw      offset _TEXT:IOT_BadT  ; fd
 375         dw      offset _TEXT:IOT_BadT  ; fe
 376         dw      offset _TEXT:IOT_BadT  ; ff
 377
 378 ;******************************************************************************
 379 ;   IOT_BadT - GP fault on Unknown I/O address
 380 ;
 381 ;   DESCRIPTION:    This routine is entered by being in the IOTrap_Tab above
 382 ;               and also for I/O ports which are not LIM(DMA) ports and are not
 383 ;               emulated by IOT_OEM routine below and the first 10 bits of the
 384 ;               address is greater than 100h. Note that only the first 10 bits
 385 ;               of the port (times 2) is passed in BX.  If the entire port
 386 ;               address is desired, it is available on the stack as the value
 387 ;               which is popped into DX.
 388 ;
 389 ;   ENTRY: Protected Mode Ring 0
 390 ;               return address, DX, DS, return address on stack
 391 ;               AL = byte to output to port.
 392 ;               BX == 2 * port address(either 0-1FE or 200-7FE)
 393 ;               DX == 0  => Emulate input
 394 ;                  <> 0  => Emulate output
 395 ;               DS = DGROUP
 396 ;               SS:BP = points to stack frame on entry to GP fault handler
 397 ;
 398 ;
 399 ;   EXIT:  Protected Mode Ring 0
 400 ;               First return address, pop'd from stack.
 401 ;               DX and DS restored from stack.
 402 ;               BX = DX on entry
 403 ;               STC => I/O NOT emulated.
 404 ;
 405 ;   WARNING:***********
 406 ;           This routine is closely allied with IOTrap which is in IOTrap.
 407 ;           It is assumed that IOTrap puts the stack in a certain state!
 408 ;           ***********
 409
 410 ;   USED:  Flags
 411 ;   STACK:
 412 ;------------------------------------------------------------------------------
 413 ;
 414 IOT_BadT        proc    near
 415         pop     bx              ;   dump return address
 416         mov     bx,dx           ; restore BX
 417         pop     dx              ; restore DX(port address)
 418         pop     ds              ; restore DS
 419         stc                     ;   port not emulated !
 420         ret                     ;  and return
 421 IOT_BadT        endp
 422
 423 ;******************************************************************************
 424 ;   IOT_OEM - Handles OEM specific I/O traps
 425 ;
 426 ;   ENTRY: Protected Mode Ring 0
 427 ;               AL = byte to output to port.
 428 ;               DX = port address for I/O.
 429 ;               SS:BP = points to stack frame on entry to GP fault handler
 430 ;               BX = 0 => Emulate Input.
 431 ;                  <>0 => Emulate Output.
 432 ;               DS = DGROUP
 433 ;               stack: near return to IOTrap, DX, DS, near return from IOTrap
 434 ;
 435 ;   EXIT:  Protected Mode Ring 0
 436 ;               Either emulate I/O and pop return, DX, DS from stack and RET
 437 ;                   with CF = 1(CF = 0 if I/O is to be ignored!?!?).
 438 ;               Or just return(no emulation done)
 439 ;
 440 ;
 441 ;   WARNING:***********
 442 ;           This routine is closely allied with IOTrap.
 443 ;           It assumes that the stack is in a certain state!
 444 ;           ***********
 445 ;
 446 ;
 447 ;   USED:  Flags
 448 ;   STACK:
 449 ;------------------------------------------------------------------------------
 450 IOT_OEM proc    near
 451 ;       cmp     dx,????
 452 ;       jnz     NoEmulation
 453 ;       or      bx,bx
 454 ;       jnz     NoEmulation
 455 ;       mov     al,????         ;emulate input
 456 ;       pop     dx              ;remove return
 457 ;       pop     dx              ;restore DX
 458 ;       pop     ds              ;restore DS
 459 ;       ret                     ;return from IOTRAP
 460 ;
 461 ;NoEmulation:
 462         ret                     ; no emulation
 463 IOT_OEM endp
 464
 465
 466 _TEXT   ends
 467
 468         end
 469 \1a