kernel.c

   1 #include "link.h"
   2 #include "stm32f411.h"
   3
   4 static const char *text[] = {
   5   "hello, friend.\r\n",
   6   "hello, friend?\r\n",
   7   "that's lame.\r\n",
   8   "maybe i should give you a name.\r\n",
   9   "but that's a slippery slope.\r\n",
  10   "you're only in my head.\r\n",
  11   "we have to remember that.\r\n",
  12   "shit.\r\n",
  13   "it's actually happening, i'm talking to an imaginary person.\r\n\n"
  14 };
  15
  16 static void
  17 reset_handler (void)
  18 {
  19   unsigned int *src, *dst;
  20   unsigned int line, off;
  21
  22   /* Relocate .data section to SRAM  */
  23   src = &_data_lma_start;
  24   dst = &_data_vma_start;
  25
  26   while (dst < &_data_vma_end)
  27     *(dst++) = *(src++);
  28
  29   /* Initialize .bss section  */
  30   dst = &_bss_vma_start;
  31
  32   while (dst < &_bss_vma_end)
  33     *(dst++) = 0;
  34
  35   /*  SYSCLK setup  ---------------------------------------------------------  */
  36
  37   /* HSEBYP: HSE clock bypass  */
  38   *RCC_CR &= ~(1u << 18); /* 0: HSE oscillator not bypassed  */
  39   /* HSEON: HSE clock enable  */
  40   *RCC_CR |= (1u << 16); /* 1: HSE oscillator ON  */
  41   /* HSERDY: HSE clock ready flag  */
  42   while (!(*RCC_CR & (1u << 17))); /* 0: HSE oscillator not ready  */
  43   /* SW: System clock switch  */
  44   *RCC_CFGR &= ~(0b11u); /* Clear SW bits  */
  45   *RCC_CFGR |= (0b01u); /* 01: HSE oscillator selected as system clock  */
  46   /* SWS: System clock switch status  */
  47   while ((*RCC_CFGR & (0b11u << 2)) != (0b01u << 2)); /* 01: HSE oscillator used
  48                                                          as the system clock  */
  49   /* HSION: Internal high-speed clock enable  */
  50   *RCC_CR &= ~(1u); /* 0: HSI oscillator OFF  */
  51
  52   /*  UART setup  -----------------------------------------------------------  */
  53
  54   /* GPIOAEN: IO port A clock enable  */
  55   *RCC_AHB1ENR |= (1u); /* 1: IO port A clock enabled  */
  56   /* MODERy[1:0]: Port x configuration bits (y = 0..15)  */
  57   *GPIOA_MODER &= ~(0b1111u << 18); /* Clear PA9 and PA10 bits  */
  58   *GPIOA_MODER |= (0b1010u << 18); /* 10: Alternate function mode  */
  59   /* AFRHy: Alternate function selection for port x bit y (y = 8..15)  */
  60   *GPIOA_AFRH &= ~(0b11111111u << 4); /* Clear PA9 and PA10 bits  */
  61   *GPIOA_AFRH |= (0b01110111u << 4); /* 0111: AF7  */
  62
  63   /* PA9: USART1_TX
  64    * PA10: USART1_RX  */
  65
  66   /* USART1EN: USART1 clock enable  */
  67   *RCC_APB2ENR |= (1u << 4); /* 1: USART1 clock enabled  */
  68   /* UE: USART enable  */
  69   *USART1_CR1 |= (1u << 13); /* 1: USART enable  */
  70   /* M: Word length  */
  71   *USART1_CR1 &= ~(1u << 12); /* 0: 1 Start bit, 8 Data bits, n Stop bit  */
  72   /* PCE: Parity control enable  */
  73   *USART1_CR1 &= ~(1u << 10); /* 0: Parity control disabled  */
  74   /* STOP: STOP bits  */
  75   *USART1_CR2 &= ~(0b11u << 12); /* 00: 1 Stop bit  */
  76   /* Clock frequency: 25MHz
  77    * Desired baud rate: 1.2 KBps
  78    * USARTDIV = 1302.0625  */
  79   *USART1_BRR = (1302u << 4) | 1u; /* mantissa and fraction (/16)  */
  80   /* TE: Transmitter enable  */
  81   *USART1_CR1 |= (1u << 3); /* 1: Transmitter is enabled  */
  82
  83   /*  LED setup  ------------------------------------------------------------  */
  84
  85   /* GPIOCEN: IO port C clock enable  */
  86   *RCC_AHB1ENR |= (1u << 2); /* 1: IO port C clock enabled  */
  87   /* MODERy[1:0]: Port x configuration bits (y = 0..15)  */
  88   *GPIOC_MODER &= ~(0b11u << 26); /* Clear PC13 bits  */
  89   *GPIOC_MODER |= (1u << 26); /* 01: General purpose output mode  */
  90
  91   /* PC13: 0 = LED on
  92    *       1 = LED off  */
  93
  94   /*  Test UART and LED  ----------------------------------------------------  */
  95
  96   while (1)
  97     {
  98       for (line = 0; line < sizeof text / sizeof *text; ++line)
  99         {
 100           /* Print current line  */
 101           off = 0;
 102           while (text[line][off])
 103             {
 104               /* TXE: Transmit data register empty  */
 105               while (!(*USART1_SR & (1u << 7))); /* 0: Data is not transferred
 106                                                     to the shift register  */
 107
 108               /* DR[8:0]: Data value  */
 109               *USART1_DR = text[line][off++];
 110             }
 111
 112           /* TC: Transmission complete  */
 113           while (!(*USART1_SR & (1u << 6))); /* 0: Transmission is not
 114                                                 complete  */
 115
 116           /* Blink LED  */
 117           *GPIOC_ODR ^= (1u << 13);
 118         }
 119     }
 120 }
 121
 122 __attribute__ ((section (".vector_table"), used))
 123 static unsigned long const vector_table[] = {
 124   (unsigned long) &_sram_end,
 125   (unsigned long) reset_handler,
 126 };