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wirehaze git hosting - stm32f411ceu6.git/blob - uart.c
4 /* Wait for data to be transferred into the shift register. */
8 /* TXE: Transmit data register empty */
9 while (!(*USART1_SR
& (1u << 7))); /* 0: Data is not transferred to the shift
13 /* Wait for transmission of the last frame. */
17 /* TC: Transmission complete */
18 while (!(*USART1_SR
& (1u << 6))); /* 0: Transmission is not complete */
24 /* DR[8:0]: Data value */
31 /* GPIOAEN: IO port A clock enable */
32 *RCC_AHB1ENR
|= (1u); /* 1: IO port A clock enabled */
34 /* MODERy[1:0]: Port x configuration bits (y = 0..15) */
35 *GPIOA_MODER
&= ~(0b1111u
<< 18); /* Clear PA9 and PA10 bits */
36 *GPIOA_MODER
|= (0b1010u
<< 18); /* 10: Alternate function mode */
38 /* AFRHy: Alternate function selection for port x bit y (y = 8..15) */
39 *GPIOA_AFRH
&= ~(0b11111111u
<< 4); /* Clear PA9 and PA10 bits */
40 *GPIOA_AFRH
|= (0b01110111u
<< 4); /* 0111: AF7 */
45 /* USART1EN: USART1 clock enable */
46 *RCC_APB2ENR
|= (1u << 4); /* 1: USART1 clock enabled */
48 /* UE: USART enable */
49 *USART1_CR1
|= (1u << 13); /* 1: USART enable */
52 *USART1_CR1
&= ~(1u << 12); /* 0: 1 Start bit, 8 Data bits, n Stop bit */
54 /* PCE: Parity control enable */
55 *USART1_CR1
&= ~(1u << 10); /* 0: Parity control disabled */
58 *USART1_CR2
&= ~(0b11u
<< 12); /* 00: 1 Stop bit */
60 /* Clock frequency: 25MHz
61 * Desired baud rate: 1.2 KBps */
63 /* Mantissa and fraction (/16) */
64 *USART1_BRR
= (1302u << 4) | 1u; /* USARTDIV = 1302.0625 */
66 /* TE: Transmitter enable */
67 *USART1_CR1
|= (1u << 3); /* 1: Transmitter is enabled */
71 kputs_busytc (const char *str
)