kernel.c

   1 #include "link.h"
   2 #include "stm32f411.h"
   3
   4 __attribute__ ((noreturn)) extern void kentry (void);
   5
   6 static void
   7 reset_handler (void)
   8 {
   9   unsigned int *src, *dst;
  10
  11   /* Set FAULTMASK  */
  12   asm ("cpsid f");
  13
  14   /*  Initialize .data and .bss in SRAM  ------------------------------------  */
  15
  16   /* Relocate .data section  */
  17   src = &_data_lma_start;
  18   dst = &_data_vma_start;
  19
  20   while (dst < &_data_vma_end)
  21     *(dst++) = *(src++);
  22
  23   /* Initialize .bss  */
  24   dst = &_bss_vma_start;
  25
  26   while (dst < &_bss_vma_end)
  27     *(dst++) = 0;
  28
  29   /*  LED setup  ------------------------------------------------------------  */
  30
  31   /* GPIOCEN: IO port C clock enable  */
  32   *RCC_AHB1ENR |= (1u << 2); /* 1: IO port C clock enabled  */
  33   /* MODERy[1:0]: Port x configuration bits (y = 0..15)  */
  34   *GPIOC_MODER &= ~(0b11u << 26); /* Clear PC13 bits  */
  35   *GPIOC_MODER |= (1u << 26); /* 01: General purpose output mode  */
  36
  37   /* PC13: 0 = LED on
  38    *       1 = LED off  */
  39
  40   /*  SYSCLK setup  ---------------------------------------------------------  */
  41
  42   /* HSEBYP: HSE clock bypass  */
  43   *RCC_CR &= ~(1u << 18); /* 0: HSE oscillator not bypassed  */
  44   /* HSEON: HSE clock enable  */
  45   *RCC_CR |= (1u << 16); /* 1: HSE oscillator ON  */
  46   /* HSERDY: HSE clock ready flag  */
  47   while (!(*RCC_CR & (1u << 17))); /* 0: HSE oscillator not ready  */
  48   /* SW: System clock switch  */
  49   *RCC_CFGR &= ~(0b11u); /* Clear SW bits  */
  50   *RCC_CFGR |= (0b01u); /* 01: HSE oscillator selected as system clock  */
  51   /* SWS: System clock switch status  */
  52   while ((*RCC_CFGR & (0b11u << 2)) != (0b01u << 2)); /* 01: HSE oscillator used
  53                                                          as the system clock  */
  54   /* HSION: Internal high-speed clock enable  */
  55   *RCC_CR &= ~(1u); /* 0: HSI oscillator OFF  */
  56
  57   /*  UART setup  -----------------------------------------------------------  */
  58
  59   /* GPIOAEN: IO port A clock enable  */
  60   *RCC_AHB1ENR |= (1u); /* 1: IO port A clock enabled  */
  61   /* MODERy[1:0]: Port x configuration bits (y = 0..15)  */
  62   *GPIOA_MODER &= ~(0b1111u << 18); /* Clear PA9 and PA10 bits  */
  63   *GPIOA_MODER |= (0b1010u << 18); /* 10: Alternate function mode  */
  64   /* AFRHy: Alternate function selection for port x bit y (y = 8..15)  */
  65   *GPIOA_AFRH &= ~(0b11111111u << 4); /* Clear PA9 and PA10 bits  */
  66   *GPIOA_AFRH |= (0b01110111u << 4); /* 0111: AF7  */
  67
  68   /* PA9: USART1_TX
  69    * PA10: USART1_RX  */
  70
  71   /* USART1EN: USART1 clock enable  */
  72   *RCC_APB2ENR |= (1u << 4); /* 1: USART1 clock enabled  */
  73   /* UE: USART enable  */
  74   *USART1_CR1 |= (1u << 13); /* 1: USART enable  */
  75   /* M: Word length  */
  76   *USART1_CR1 &= ~(1u << 12); /* 0: 1 Start bit, 8 Data bits, n Stop bit  */
  77   /* PCE: Parity control enable  */
  78   *USART1_CR1 &= ~(1u << 10); /* 0: Parity control disabled  */
  79   /* STOP: STOP bits  */
  80   *USART1_CR2 &= ~(0b11u << 12); /* 00: 1 Stop bit  */
  81   /* Clock frequency: 25MHz
  82    * Desired baud rate: 1.2 KBps
  83    * USARTDIV = 1302.0625  */
  84   *USART1_BRR = (1302u << 4) | 1u; /* mantissa and fraction (/16)  */
  85   /* TE: Transmitter enable  */
  86   *USART1_CR1 |= (1u << 3); /* 1: Transmitter is enabled  */
  87
  88   /*  Jump to kernel entry code  --------------------------------------------  */
  89
  90   /* Clear FAULTMASK  */
  91   asm ("cpsie f");
  92
  93   kentry ();
  94 }
  95
  96 __attribute__ ((section (".vector_table"), used))
  97 static unsigned long const vector_table[] = {
  98   (unsigned long) &_sram_end,
  99   (unsigned long) reset_handler,
 100 };