]>
wirehaze git hosting - stm32f411ceu6.git/blob - sysclk.c
a106774ac2701bde180ebe032a6b677453770285
7 /* HSEBYP: HSE clock bypass */
8 *RCC_CR
&= ~(1u << 18); /* 0: HSE oscillator not bypassed */
10 /* HSEON: HSE clock enable */
11 *RCC_CR
|= (1u << 16); /* 1: HSE oscillator ON */
13 /* HSERDY: HSE clock ready flag */
14 while (!(*RCC_CR
& (1u << 17))); /* 0: HSE oscillator not ready */
16 /* SW: System clock switch */
17 *RCC_CFGR
&= ~(0b11u
); /* Clear SW bits */
18 *RCC_CFGR
|= (0b01u
); /* 01: HSE oscillator selected as system clock */
20 /* SWS: System clock switch status */
21 while ((*RCC_CFGR
& (0b11u
<< 2)) != (0b01u
<< 2)); /* 01: HSE oscillator used
22 as the system clock */
23 /* HSION: Internal high-speed clock enable */
24 *RCC_CR
&= ~(1u); /* 0: HSI oscillator OFF */