usart wip

diff --git a/kernel.c b/kernel.c
index 28d576d39c14642470c98d38824cd3621e75b100..6f66e49640c08b006a41bd93c87ce39135e5f692 100644 (file)
--- a/kernel.c
+++ b/kernel.c
@@ -1,13 +1,7 @@
-extern unsigned int _sram_end;
-extern unsigned int _data_vma_start;
-extern unsigned int _data_vma_end;
-extern unsigned int _data_lma_start;
-extern unsigned int _bss_vma_start;
-extern unsigned int _bss_vma_end;
+#include "link.h"
+#include "stm32f411.h"

 
 

-#define RCC_AHB1 ((volatile unsigned int * const) 0x40023830)
-#define GPIOC_MODER ((volatile unsigned int * const) 0x40020800)
-#define GPIOC_ODR ((volatile unsigned int * const) 0x40020814)
+const char msg[] = "blink ";

 
 static void
 delay (void)
 
 static void
 delay (void)


@@ -20,6 +14,7 @@ static void
 reset_handler (void)
 {
   unsigned int *src, *dst;
 reset_handler (void)
 {
   unsigned int *src, *dst;

+  unsigned int off;

 
   /* relocate .data to sram  */
   src = &_data_lma_start;
 
   /* relocate .data to sram  */
   src = &_data_lma_start;


@@ -34,19 +29,46 @@ reset_handler (void)
   while (dst < &_bss_vma_end)
     *(dst++) = 0;
 
   while (dst < &_bss_vma_end)
     *(dst++) = 0;
 

-  /* blink blink  */
-  *RCC_AHB1 |= (1u << 2);
+  /* (todo) usart pin setup (alt func and enable port clock)  */
+
+  /* UE: USART enable  */
+  *USART_CR1 |= (1u << 13); /* 1: USART enable  */
+  /* M: Word length  */
+  *USART_CR1 &= ~(1u << 12); /* 0: 1 Start bit, 8 Data bits, n Stop bit  */
+  /* STOP: STOP bits  */
+  *USART_CR2 &= ~(3u << 12); /* 00: 1 Stop bit  */
+  /* the clock frequnecy is 16mhz initially, so for a baud rate of 115.2 KBps we
+   * need to set USARTDIV=8.6875  */
+  *USART_BRR = (8u << 4) | 11; /* mantissa and fraction (/16)  */
+  /* TE: Transmitter enable  */
+  *USART_CR1 |= (1u << 3); /* 1: Transmitter is enabled  */
+
+  /* blink blink setup  */
+  *RCC_AHB1ENR |= (1u << 2);

   *GPIOC_MODER &= ~(3u << 26);
   *GPIOC_MODER |= (1u << 26);
 
   while (1)
     {
   *GPIOC_MODER &= ~(3u << 26);
   *GPIOC_MODER |= (1u << 26);
 
   while (1)
     {

+      /* speak  */
+      off = 0;
+      do
+        {
+          /* TXE: Transmit data register empty  */
+          if (!(*USART_SR & (1u << 7)))
+            continue;
+
+          *USART_DR = msg[off++];
+        }
+      while (off < sizeof msg);
+
+      /* blink  */

       *GPIOC_ODR ^= (1u << 13);
       delay ();
     }
 }
 
       *GPIOC_ODR ^= (1u << 13);
       delay ();
     }
 }
 

-__attribute__ ((section (".vtbl"), used))
+__attribute__ ((section (".vector_table"), used))

 static unsigned long const vector_table[] = {
   (unsigned long) &_sram_end,
   (unsigned long) reset_handler,
 static unsigned long const vector_table[] = {
   (unsigned long) &_sram_end,
   (unsigned long) reset_handler,

diff --git a/kernel.ld b/kernel.ld
index 92a94c4ba3aa2cbc98acbe45b461e952966a5576..69d063bed96525ac474e955aeaea9475e79b5e3f 100644 (file)
--- a/kernel.ld
+++ b/kernel.ld
@@ -12,9 +12,9 @@ _sram_end = ORIGIN(sram) + LENGTH(sram);
 
 SECTIONS
 {
 
 SECTIONS
 {

-  .vtbl :
+  .vector_table :

     {
     {

-      *(.vtbl)
+      *(.vector_table)

       . = 0x400;
     } >flash
   .text :
       . = 0x400;
     } >flash
   .text :

diff --git a/link.h b/link.h
new file mode 100644 (file)
index 0000000..703a70b
--- /dev/null
+++ b/link.h
@@ -0,0 +1,14 @@
+#ifndef _LINK_H_
+#define _LINK_H_
+
+extern unsigned int _flash_start;
+extern unsigned int _flash_end;
+extern unsigned int _sram_start;
+extern unsigned int _sram_end;
+extern unsigned int _data_vma_start;
+extern unsigned int _data_vma_end;
+extern unsigned int _data_lma_start;
+extern unsigned int _bss_vma_start;
+extern unsigned int _bss_vma_end;
+
+#endif /* _LINK_H_  */

diff --git a/stm32f411.h b/stm32f411.h
new file mode 100644 (file)
index 0000000..57ceb90
--- /dev/null
+++ b/stm32f411.h
@@ -0,0 +1,30 @@
+#ifndef _STM32F411_H_
+#define _STM32F411_H_
+
+/* (todo) boundary check?  */
+#define _MMIO_(base, offset) ((volatile unsigned int * const) (base + offset))
+
+
+/*  AHB1  -------------------------------------------------------------------  */
+
+#define RCC 0x40023800
+#define RCC_AHB1ENR _MMIO_ (RCC, 0x30)
+
+#define GPIOC 0x40020800
+#define GPIOC_MODER _MMIO_ (GPIOC, 0x00)
+#define GPIOC_ODR _MMIO_ (GPIOC, 0x14)
+
+
+/*  APB2  -------------------------------------------------------------------  */
+
+#define USART 0x40011000 /* USART1  */
+#define USART_SR _MMIO_ (USART, 0x00)
+#define USART_DR _MMIO_ (USART, 0x04)
+#define USART_BRR _MMIO_ (USART, 0x08)
+#define USART_CR1 _MMIO_ (USART, 0x0c)
+#define USART_CR2 _MMIO_ (USART, 0x10)
+#define USART_CR3 _MMIO_ (USART, 0x14)
+#define USART_GTPR _MMIO_ (USART, 0x18)
+
+
+#endif /* _STM32F411_H_  */